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lt3507 1 3507fa features applications description triple monolithic step-down regulator with ldo the lt ? 3507 is a triple, current mode, dc/dc converter with internal power switches and a low dropout regulator. the switching converters are step-down converters capable of generating one 2.4a output and two 1.5a outputs. all three converters are synchronized to a single oscillator. the 2.4a output runs with opposite phase to the other two converters, reducing input ripple current. each regulator has independent shutdown and soft-start circuits, and generates a power good signal when its output is in regu- lation, easing power supply sequencing and interfacing with microcontrollers and dsps. the switching frequency is set with a single resistor yielding a range of 250khz to 2.5mhz. the high switching frequency allows the use of small inductors and capacitors resulting in a very small triple output supply. the constant switching frequency, combined with low impedance ceramic capaci- tors, results in low, predictable output ripple. with its wide input voltage range of 4v to 36v, the lt3507 regulates a broad array of power sources including 5v logic rails, unregulated wall transformers, lead acid batteries and distributed power supplies. n wide input range: 4v to 36v n one 2.4a and two 1.5a output switching regulators with internal power switches n low dropout linear regulator with external transistor n antiphase switching reduces ripple n independent run, tracking/soft-start, and power good indicators ease supply sequencing n uses small inductors and ceramic capacitors n adjustable, 250khz to 2.5mhz switching frequency, synchronizable over the full range n user programmable overvoltage and undervoltage lockouts n thermally enhanced, 38-lead 5mm 7mm qfn package n dsl and cable modems n distributed power regulation n dsp power n automotive typical application v in1 boost1 boost3 sw3 fb3 v c3 bias drive fb4 sw1 fb1 v c1 boost2 0.22 f 10.2k 53.6k v in 6v to 36v v out3 5v 1.5a v in2 v in3 sw2 fb2 v c2 gnd lt3507 22 f 24.3k 3507 ta01a 107k 11.5k v out2 3.3v 1.3a v out4 2.5v 0.2a r t /sync 680pf 15 h 2.2 f 22 f f sw = 450khz 0.22 f 0.22 f 15k 18.7k v out1 1.8v 2.4a 100 f 18.7k 680pf 4.7 h 24.3k 1000pf 16.2k 11.5k 35.7k 10 h 22 f v out2 start-up waveformscoincident tracking 5v, 3.3v, 2.5v and 1.8v step-down regulator 1v/div v out1 v out2 v out3 v out4 1ms/div 3507 ta01b l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
lt3507 2 3507fa pin configuration absolute maximum ratings v in pins ...................................................... ?0.3v to 36v boost pins ..............................................................55v boost above sw .....................................................25v pgood pins ..............................................................36v bias pin ....................................................................16v trk/ss, v c , fb, r t /sync pins ...................................6v run, ovlo, uvlo pins ........................................... v in1 drive pin ...................................................................5v operating junction temperature range (notes 2, 5) lt3507e, lt3507i .............................. ?40c to 125c lt3507h ............................................ ?40c to 150c storage temperature range ................... ?65c to 150c (note 1) 13 14 15 16 top view 39 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1boost1 v in1 v in1 v insw ovlo uvlo v c1 trk/ss1 fb1 pgood1 pgood2 pgood3 v in2 v in2 sw2 sw2 boost2 trk/ss4 fb4 drive v c2 fb2 trk/ss2 fb3 sw1 sw1 v in3 v in3 sw3 sw3 boost3 r t /sync run1 run2 run3 bias trk/ss3 v c3 23 22 21 20 9 10 11 12 ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb parameter conditions min typ max units minimum operating voltage internal uvlo on v in1 l 3.8 4 v input quiescent current not switching, v bias = 3.3v 2 3.5 ma bias quiescent current not switching, v bias = 3.3v 5 7.5 ma shutdown current v run1,2,3 = 0v 1 a reference voltage line regulation 5v < v in1 < 36v 0.01 %/v the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in1 , v in2 , v in3 = 12v, v boost1 , v boost2 , v boost3 = 17v, unless otherwise noted. (note 2) lead free finish tape and reel part marking* package description temperature range lt3507euhf#pbf lt3507iuhf#pbf lt3507huhf#pbf lt3507euhf#trpbf lt3507iuhf#trpbf lt3507huhf#trpbf 3507 3507 3507 38-lead (5mm 7mm) plastic qfn 38-lead (5mm 7mm) plastic qfn 38-lead (5mm 7mm) plastic qfn ?40c to 125c ?40c to 125c ?40c to 150c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. *for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information electrical characteristics
lt3507 3 3507fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in1 , v in2 , v in3 = 12v, v boost1 , v boost2 , v boost3 = 17v, unless otherwise noted. (note 2) parameter conditions min typ max units v c source current v c = 0.6v 20 a v c sink current v c = 0.6v 30 a v c clamp voltage 1.7 v switching frequency r t = 40.2k l 0.9 1.1 mhz switching phase sw1 to sw2,3, r t = 40.2k 180 deg foldback frequency v fb = 0v, r t = 40.2k 120 khz frequency shift threshold on fb 0.4 v run threshold 1 1.5 v pgood output voltage low i pgood = 200a 0.2 0.4 v pgood pin leakage v pgood = 2v 10 400 na pgood threshold offset v fb rising 58 80 105 mv feedback pin voltage l 788 800 812 mv feedback pin bias current l C50 C500 na error ampli? er transconductance 330 s error ampli? er voltage gain 500 v/v v c switching threshold 0.9 v switch leakage current 0.01 10 a minimum boost voltage above switch (note 4) 1.8 2.5 v converter 1 v c1 to switch current gain 5a/v switch 1 current limit (note 3) duty cycle = 15% l 3 4.3 6 a switch 1 v cesat i sw1 = 2a 400 600 mv boost1 operating current i sw1 = 2a 40 60 ma converter 2 v c2 to switch current gain 3.6 a/v switch 2 current limit (note 3) duty cycle = 15% l 2 2.9 4 a switch 2 v cesat i sw2 = 1.5a 350 500 mv boost2 operating current i sw2 = 1.5a 40 60 ma converter 3 v c3 to switch current gain 3.6 a/v switch 3 current limit (note 3) duty cycle = 15% l 2 2.9 4 a switch 3 v cesat i sw3 = 1.5a 350 500 mv boost3 operating current i sw3 = 1.5a 40 60 ma ldo regulator feedback pin voltage l 788 800 812 mv feedback pin bias current C150 C500 na error ampli? er voltage gain 1100 v/v line regulation v in from 5v to 36v 0.05 %/v
lt3507 4 3507fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in1 , v in2 , v in3 = 12v, v boost1 , v boost2 , v boost3 = 17v, unless otherwise noted (note 2) parameter conditions min typ max units load regulation i drive from 0.1ma to 10ma 0.005 %/ma drive output current limit l 10 15 22.5 ma dropout voltage, v in1 to drive i drive = 10ma 1.7 2.0 v dropout voltage, bias to drive i drive = 10ma 0.5 0.8 v over/undervoltage lockout undervoltage lockout threshold 1.15 1.20 1.25 v overvoltage lockout threhold 1.15 1.20 1.25 v undervoltage lockout hysteresis current v(uvlo) < 1.2v 7 10 13 a overvoltage lockout hysteresis current v(ovlo) > 1.2v C7 C10 C13 a input bias current (ovlo and uvlo) C100 C200 na note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3507e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3507i is guaranteed to meet performance speci? cations from C40c to 125c junction temperature. the lt3507h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 4: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating range when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
lt3507 5 3507fa typical performance characteristics v fb vs temperature frequency vs r t frequency vs temperature frequency vs v fb (foldback) i trk/ss vs temperature ef? ciency vs load current, channel 1, v out = 1.8v switch v cesat vs switch current, channels 1, 2 and 3 boost pin current vs switch current, channels 1, 2 and 3 ef? ciency vs load current, channels 2 and 3, v out = 3.3v i out (a) 0 efficiency (%) 90 80 60 70 50 40 2 1 3507 g01 2.5 1.5 0.5 v in = 6v v in = 12v v in = 36v t a = 25c f sw = 450khz i out (a) 0 efficiency (%) 100 80 90 60 70 50 40 1.2 0.6 3507 g02 1.5 0.9 0.3 v in = 6v v in = 12v v in = 36v t a = 25c f sw = 450khz i sw (a) 0 v sw (v) 0.6 0.4 0.5 0.2 0.3 0.1 0 2.5 1 3507 g03 3 1.5 2 0.5 channels 2 & 3 channel 1 t a = 25c i sw (a) 0 i boost (ma) 100 80 70 60 50 40 90 20 30 10 0 2.5 1 3507 g04 3 1.5 2 0.5 channels 2 & 3 channel 1 t a = 25c temperature (c) C50 v fb (mv) 805 803 802 801 800 799 804 797 798 796 795 130 C10 3507 g05 150 90 70 50 30 110 C30 r t (k) frequency (mhz) 3507 g06 2.5 0.25 10 100 t a = 25c temperature (c) C50 frequency deviation (%) 0.5 C0.5 C1.0 C1.5 0.0 C2.0 130 C10 3507 g07 150 90 70 50 30 110 C30 v fb (v) 0 frerquency (khz) 1200 800 600 400 200 1000 0 0.8 0.4 3507 g08 1 0.6 0.2 r t = 40.2k t a = 25c temperature (c) C50 i trk/ss (a) 1.30 1.26 1.24 1.22 1.28 1.20 130 C10 3507 g09 150 90 70 50 30 110 C30
lt3507 6 3507fa typical performance characteristics v in1 -v insw voltage drop vs i vinsw current limit vs duty cycle minimum on-time vs i sw run threshold vs temperature minimum off-time vs i sw temperature (c) C50 run threshold (v) 1.2 1.0 0.6 0.4 0.2 0.8 0.0 130 C10 3507 g10 150 90 70 50 30 110 C30 i vinsw (ma) 0 v in Cv insw (v) 0.40 0.20 0.30 0.35 0.25 0.15 0.05 0.10 0.00 0.8 0.4 3507 g11 1.0 0.6 0.2 t a = 25c duty cycle (%) 0 i lim (a) 4.5 2.0 3.0 3.5 4.0 2.5 1.5 0.5 1.0 0.0 80 40 3507 g12 100 60 20 channel 1 channels 2 & 3 t a = 25c i sw (a) 0 minimum on-time (ns) 250 150 200 50 100 0 3507 g13 3 2 1 150c 25c C40c i sw (a) 0 minimum off-time (ns) 200 150 50 100 0 2 2.5 1 3507 g14 3 1.5 0.5 150c 25c C40c
lt3507 7 3507fa pin functions boost1, boost2, boost3 (pins 1, 27, 32): the boost pins are used to provide drive voltages, higher than the input voltage, to the internal bipolar npn power switches. these pins must be tied through a diode from v out , v in or another supply greater than 2.5v. v in1 (pins 2, 3): the v in1 pins supply power to the internal switch of the 2.4a regulator and to the lt3507s internal reference and start-up circuitry. these pins must be locally bypassed (note 6). v insw (pin 4): the v insw pin is a switched v in1 for the user programmable undervoltage and overvoltage detec- tion. it is connected to v in1 when any of the run pins are pulled high, and high impedance when all run pins are low or open. ovlo (pin 5): the lt3507 goes into overvoltage shutdown when this pin goes above 1.2v. if unused, the ovlo pin should be tied to gnd. uvlo (pin 6): the lt3507 goes into undervoltage shutdown when this pin drops below 1.2v. if unused, the uvlo pin should be tied to v insw . v c1 , v c2 , v c3 (pins 7, 23, 19): the v c pins are the outputs of the internal error amps. the voltages on these pins control the peak switch currents. these pins are normally used to compensate the control loops. each switching regulator can be shut down by pulling its respective v c pin to ground with an nmos or npn transistor. trk/ss1, trk/ss2, trk/ss3, trk/ss4 (pins 8, 21, 18, 26): the trk/ss pins allow a regulator to track the output of another regulator. when the trk/ss pin is below 0.8v, the fb pin regulates to the trk/ss voltage. this pin can also be used as a soft-start by connecting a capacitor from trk/ss to ground. the trk/ss pins should be left open if neither feature is used. fb1, fb2, fb3 (pins 9, 22, 20): the fb pins are the nega- tive inputs of the error ampli? ers. the lt3507 regulates each feedback pin to the lesser of 0.8v or the trk/ss pin voltage. connect the feedback resistor divider taps to these pins. note 6: v inx pins that are connected together may share a bypass capacitor. pgood1, pgood2, pgood3 (pins 10, 11, 12): the pgood pins are the open-collector outputs of an internal comparator. pgood remains low until the fb pin is within 10% of the ? nal regulation voltage. as well as indicating output regulation, the pgood pins can sequence the switching regulators. these pins must be left unconnected if unused. the pgood outputs are valid when v in is greater than 3.5v and any of the run pins are high. they are not valid when all run pins are low. r t /sync (pin 13): the r t /sync pin requires a resistor to ground or a clock signal to set the operating frequency of the lt3507. run1, run2, run3 (pins 14, 15, 16): the run pins are used to shut down the individual switching regulators. when all three run pins are low, the lt3507 shuts down and draws less than 1a from v in1 . bias (pin 17): the bias pin supplies the current to the lt3507s internal regulator. this pin should be tied to the lowest available voltage source above 3v (either v in , v out or any other available supply). the ldo pass transistors base current is supplied from the bias pin if it is at least 0.8v above the ldo drive output. drive (pin 24): the drive pin provides the base drive for an external npn transistor used for the ldo regulator. fb4 (pin 25): the fb4 pin is the negative input to the ldo error ampli? er. it is regulated to 0.8v through the ldo feedback resistor divider. v in2 (pins 30, 31)/v in3 (pins 35, 36 ): the v in2 and v in3 pins supply power to the internal switches of the 1.5a con- verters. these pins must be locally bypassed (note 6). sw1 (pins 37, 38)/sw2 (pins 28, 29)/sw3 (pins 33, 34): the sw pins are the outputs of the internal power switches. connect these pins to the inductors and switch- ing diodes. exposed pad (pin 39): ground. the underside exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. the exposed pad must be soldered to a grounded pad on the circuit board for proper operation.
lt3507 8 3507fa block diagram figure 1. lt3507 block diagram with typical external components C + C + C + C + C + C + C + C + + + C C 1.2v ovlo v insw uvlo drive v in4 v out4 0.8v trk/ss4 fb4 boost sw fb trk/ss 3507 f01 v in shdn v inx c in c3 v outx c1 d2 d1 0.8v 80mv one of three step-down regulators error amp i limit clamp 1.25a l1 r1 r2 undervoltage detection thermal shutdown channel shutdown 0.9v c1 0.4v v c r c c c c f pgood 1.7v slope clk s q r + slave osc + + run1 bias v in1 run2 run3 r t /sync gnd master osc int reg and ref clk1 clk2 clk3
lt3507 9 3507fa operation the lt3507 contains three independent, constant fre- quency, current mode, switching regulators with internal power switches plus a low dropout linear regulator. the three regulators share common circuitry including input source, voltage reference and oscillator, but are otherwise independent. operation can be best understood by refer- ring to the block diagram (figure 1). if the run pins are tied to ground, the lt3507 is shut down and draws <1a from the input source tied to v in1 . if any of the run pins are driven above 1v, the internal bias circuits turn on, including the internal regulator, reference, and master oscillator. each switching regulator will only begin to operate when its corresponding run pin reaches >1.25v. the master oscillator generates three clock signals, with the signal for channel 1 out of phase by 180. the three switchers are current mode regulators. instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. compared to voltage mode control, cur- rent mode control improves loop dynamics and provides cycle-by-cycle current limit. the block diagram shows only one of the three step-down switching regulators. a pulse from the slave oscillator sets the rs ? ip-? op and turns on the internal npn bipo- lar power switch. current in the switch and the external inductor begins to increase. when this current exceeds a level determined by the voltage at v c , current comparator c1 resets the ? ip-? op, turning off the switch. the current in the inductor ? ows through the external schottky diode and begins to decrease. the cycle begins again at the next pulse from the oscillator. in this way, the voltage on the v c pin controls the current through the inductor to the output. the internal error ampli? er regulates the output voltage by continually adjusting the v c pin voltage. the threshold for switching on the v c pin is >1v and an active clamp of 1.8v limits the output current. each switcher contains an extra, independent oscillator to perform frequency foldback during overload conditions. this slave oscillator is normally synchronized to the master oscillator. a comparator senses when v fb is less than 50% of its regulated value and switches the regulator from the master oscillator to a slower slave oscillator. v fb is less than 50% of its regulated value during start-up, short-circuit and overload conditions. frequency foldback helps limit switch current under these conditions. the trk/ss pins override the 0.8v reference for the fb pins when the trk/ss pins are below 0.8v. this allows either coincident or ratiometric supply tracking on start-up as well as a soft-start capability. the switch drivers operate either from v in or from the boost pin. an external capacitor and diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to saturate the internal bipolar npn power switch for ef? cient operation. the bias pin allows the internal circuitry to draw its current from a lower voltage supply than the input, also reducing power dissipation and increasing ef? ciency. if the voltage on the bias pin falls below 3v, then its quiescent current will ? ow from v in . a power good comparator trips when the fb pin is at 90% of its regulated value. the pgood output is an open-collector transistor that is off when the output is in regulation, allowing an external resistor to pull the pgood pin high. power good is valid when the lt3507 is enabled and v in > 3.5v. the ldo regulator uses an external npn pass transistor to form a linear regulator. the loop is internally compensated to be stable with a load capacitance of 2.2f or greater. the ldo is disabled when all three of the run pins are low. the overvoltage and undervoltage detection shuts down the lt3507 if the input voltage goes above or below re- sistor programmable thresholds. the hysteresis of these detectors is also resistor programmable.
lt3507 10 3507fa applications information step-down considerations fb resistor network the output voltage is programmed with a resistor divider (refer to the block diagram) between the output and the fb pin. choose the resistors according to: r1 = r2 v out 800mv ?1 ? ? ? ? ? ? the parallel combination of r1 and r2 should be 10k or less to avoid bias current errors. input voltage range the minimum operating voltage is determined either by the lt3507s internal undervoltage lockout (4v on v in1 , 3v on v in2 and v in3 ) or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = v out + v f v in ?v sw + v f where v f is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch (~0.3v at maximum load). this leads to a minimum input voltage of: v in(min) = v out + v f dc max ?v f + v sw the duty cycle is the fraction of time that the internal switch is on during a clock cycle. the maximum duty cycle is generally given by dc max = 1C t off(min) ? f sw . however, unlike most ? xed frequency regulators, the lt3507 will not switch off at the end of each clock cycle if there is suf? cient voltage across the boost capacitor (c3 in figure 1) to fully saturate the output switch. forced switch off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. this operation has the same effect as lowering the clock frequency for a ? xed off time, resulting in a higher duty cycle and lower minimum input voltage. the resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: dc max = 1 1 + 1 b where b is the output current capacity divided by the typical boost current from the boost pin current vs switch current in the typical performance characteristics section. the maximum operating voltage without pulse-skipping is determined by the minimum duty cycle dc min : v in(ps) = v out + v f dc min ?v f + v sw with dc min = t on(min) ? f sw . thus both the maximum and minimum input voltages are a function of the switching frequency and output voltages. therefore the maximum switching frequency must be set to a value that accommodates all the input and output voltage parameters and must meet both of the following criteria for each channel: f max1 = v out + v f v in(ps) ?v sw + v f ? ? ? ? ? ? ? 1 t on(min) f max2 = 1? v out + v f v in(min) ?v sw + v f ? ? ? ? ? ? ? 1 t off(min) the values of t on(min) and t off(min) are functions of i sw and temperature (see chart in the typical performance characteristics section). worst-case values for switch currents greater than 0.5a are t on(min) = 130ns (for t j > 125c t on(min) = 155ns) and t off(min) = 170ns. f max1 is the frequency at which the minimum duty cycle is exceeded. the regulator will skip on pulses in order to reduce the overall duty cycle at frequencies above f max1 . it will continue to regulate but with increased inductor current and greatly increased output ripple. the increased peak inductor current in pulse-skipping will also stress the switch transistor at high voltages and high switch- ing frequency. if the lt3507 is allowed to pulse-skip and the input voltage is greater than 20v, then the switching frequency must be kept below 1.1mhz to prevent damage to the lt3507.
lt3507 11 3507fa f max2 is the frequency at which the maximum duty cycle is exceeded. if there is suf? cient charge on the boost capacitor, the regulator will skip off periods to increase the overall duty cycle at frequencies about f max2 . it will continue to regulate but with increased inductor current and greatly increased output ripple. note that the restriction on the operating input voltage refers to steady-state limits to keep the output in regula- tion; the circuit will tolerate input voltage transients up to the absolute maximum rating. switching frequency once the upper and lower bounds for the switching frequency are found from the duty cycle requirements, the frequency may be set within those bounds. lower frequencies result in lower switching losses, but require larger inductors and capacitors. the user must decide the best trade-off. the switching frequency is set by a resistor connected from the r t /sync pin to ground, or by forcing a clock signal into r t /sync. the lt3507 applies a voltage of ~1.25v across this resistor and uses the current to set the oscillator speed. the switching frequency is given by the following formula: f sw = 55 r t + 12 where f sw is in mhz and r t is in k. the frequency sync signal will support v h logic levels from 1.8v to 5v cmos or ttl. the duty cycle is not important, but it needs a minimum on time of 100ns and a minimum off time of 100ns. if the sync circuit is to be powered from one of the lt3507 outputs there may be start-up problems if the driving gate is high impedance without a supply or pulls high or low at some intermediate supply voltage. the circuit shown in figure 2 prevents these problems by isolating the clock sync circuit until the clock is operating. the schottky diode should be a low leakage type such as the bas70 from on semi or cmod6263 from central semi. r t should be set to provide a frequency within 25% of the ? nal sync frequency. inductor selection and maximum output current the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to-peak inductor ripple current. the lt3507 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt3507 will deliver depends on the switch current limit, the inductor value and the input and output voltages. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: i l = 1? dc () v out + v f l?f where f is the switching frequency of the lt3507 and l is the value of the inductor. the peak inductor and switch current is: i swpk = i lpk = i out + i l 2 to maintain output regulation, this peak current must be less than the lt3507s switch current limit, i lim . for sw1, i lim is at least 3a at low duty cycles and decreases linearly to 2.4a at dc = 0.8. for sw2 and sw3, i lim is at least 2a for at low duty cycles and decreases linearly to 1.6a at dc = 0.8. the minimum inductance can now be calculated as: l min = 1 ? dc min 2?f ? v out + v f i lim ?i out however, its generally better to use an inductor larger than the minimum value. the minimum inductor has large ripple currents which increase core losses and require large output capacitors to keep output voltage ripple low. applications information figure 2. clock powered from lt3507 output r t /sync v out1 3507 f02 lt3507 sw1 clk clock sync v cc r t bas70 1k 470pf
lt3507 12 3507fa select an inductor greater than l min that keeps the ripple current below 30% of i lim . the inductors rms current rating must be greater than the maximum load current and its saturation current should be greater than i lpk . for highest ef? ciency, the series resistance (dcr) should be less than 0.1. table 1 lists several vendors and types that are suitable. table 1. inductors part number value (h) i sat (a) dcr ( ) height (mm) sumida cdc5d23-2r2 2.2 2.16 0.030 2.5 cdrh5d28-2r6 2.6 2.60 0.013 3.0 cdrh6d26-5r6 5.6 2.00 0.027 2.8 cdh113-100 10 2.00 0.047 3.7 coilcraft do1606t-152 1.5 2.10 0.060 2.0 lps6225-222ml 2.2 4.00 0.045 2.4 do1608c-332 3.3 2.00 0.080 2.9 mss6132-472ml 4.7 2.60 0.056 3.2 do1813p-682hc 6.8 2.20 0.080 5.0 cooper sd414-2r2 2.2 2.73 0.061 1.35 dra73-6r8-r 6.8 2.96 0.041 3.55 up1b-100 10 1.90 0.111 5.0 toko (d62f)847fy-2r4m 2.4 2.5 0.037 2.7 (d73lf)817fy-2r2m 2.2 2.7 0.03 3.0 this analysis is valid for continuous mode operation (i out > i lim /2). for details of maximum output current in discontinuous mode operation, see linear technologys application note an44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid subharmonic oscillations. this minimum inductance is: sw1:l min = v out + v f () ? 0.45 f sw sw2, sw3:l min = v out + v f () ? 0.9 f sw with l min in h and f sw in mhz. output capacitor selection the output capacitor ? lters the inductor current to generate an output with low voltage ripple. it also stores energy in order to satisfy transient loads and stabilize the lt3507s control loop. because the lt3507 operates at a high frequency, minimal output capacitance is necessary. in addition, the control loop operates well with or without the presence of output capacitor series resistance (esr). ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option. you can estimate output ripple with the following equations: v ripple = i l 8?f?c out for ceramic capacitors and v ripple = i l ? esr for electrolytic capacitors (tantalum and aluminum) where i l is the peak-to-peak ripple current in the inductor. the rms content of this ripple is very low so the rms current rating of the output capacitor is usually not of concern. it can be estimated with the formula: i c(rms) = i l 12 another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. for a 5% overshoot, this requirement indicates: c out > 10 ? l ? i lim v out ? ? ? ? ? ? 2 the low esr and small size of ceramic capacitors make them the preferred type for lt3507 applications. not all ceramic capacitors are the same, however. many of the higher value capacitors use poor dielectrics with high temperature and voltage coef? cients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and at temperature extremes. because loop stability and transient response depend on the value of c out , this loss may be unacceptable. use x7r and x5r types. applications information
lt3507 13 3507fa electrolytic capacitors are also an option. the esrs of most aluminum electrolytic capacitors are too large to deliver low output ripple. tantalum, as well as newer, lower-esr organic electrolytic capacitors intended for power supply use are suitable. chose a capacitor with a low enough esr for the required output ripple. because the volume of the capacitor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give similar ripple performance. one bene? t is that the larger capacitance may give better transient response for large changes in load current. table 2 lists several capacitor vendors. table 2. low esr surface mount capacitors vendor type series taiyo-yuden ceramic avx ceramic tantalum tps kemet tantalum tantalum organic aluminum organic t491,t494,t495 t520 a700 sanyo tantalum or aluminum organic poscap panasonic aluminum organic sp cap tdk ceramic diode selection the catch diode (d1 from figure 2) conducts current only during switch off time. average forward current in normal operation can be calculated from: i d(avg) = i out v in ?v out () v in the only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of shorted output. the diode current will then increase to the typical peak switch current. peak reverse voltage is equal to the regulator input voltage. use a diode with a reverse voltage rating greater than the input voltage. the programmable ovlo can protect the diode from excessive reverse voltage by shutting down the regulator if the input voltage exceeds the maximum rating of the diode. table 3 lists several schottky diodes and their manufacturers. table 3. schottky diodes part number v r (v) i ave (a) v f at 1a (mv) v f at 2 a (mv) on semiconductor mbrm120e 20 1 530 595 mbrm140 40 1 550 diodes inc b120 20 1 500 b140 40 1 500 b220 20 2 500 b240 40 2 500 dfls140l 40 1 550 dfls240l 40 2 550 boost pin considerations the capacitor and diode tied to the boost pin generate a voltage that is higher than the input voltage. in most cases, a small ceramic capacitor and fast switching diode (such as the cmdsh-3 or mmsd914lt1) will work well. the capacitor value is a function of the switching frequency, peak current, duty cycle and boost voltage; in general a value of (0.1f ? 1mhz/f sw ) works well. figure 3 shows three ways to arrange the boost circuit. the boost pin must be more than 2.5v above the sw pin for full ef- ? ciency. for outputs of 3.3v and higher, the standard circuit (figure 3a) is best. for outputs between 2.8v and 3.3v, use a small schottky diode (such as the bat54). for lower output voltages, the boost diode can be tied to the input (figure 3b). the circuit in figure 3a is more ef? cient because the boost pin current comes from a lower voltage source. finally, as shown in figure 3c, the anode of the boost diode can be tied to another source that is at least 3v. for example, if you are generating 3.3v and 1.8v and the 3.3v is on whenever the 1.8v is on, the 1.8v boost diode can be connected to the 3.3v output. in this case, the 3.3v output cannot be set to track the 1.8v output (see output voltage tracking). in any case, be sure that the maximum voltage at the boost pin is less than 55v and the voltage difference between the boost and sw pins is less than 25v. the minimum operating voltage of an lt3507 applica- tion is limited by the internal undervoltage lockout (4v for channel 1, 3v for channels 2 and 3) and by the applications information
lt3507 14 3507fa maximum duty cycle. the boost circuit also limits the minimum input voltage for proper start-up. if the input voltage ramps slowly, or the lt3507 turns on when the output is already in regulation, the boost capacitor may not be fully charged. because the boost capacitor charges with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load current generally goes to zero once the circuit has started. figure 4 shows a plot of minimum load to start and to run as a function of input voltage. even without an output load current, in many cases the discharged output capacitor will present a load to the switcher that will allow it to start. the boost current is generally small but can become signi? - cant at high duty cycles. the required boost current is: i boost = v out v in ? ? ? ? ? ? i out 40 ? ? ? ? ? ? converter with backup output regulator there is another situation to consider in systems where the output will be held high when the input to the lt3507 is absent. if the v in and one of the run pins are allowed applications information figure 3. generating the boost voltage figure 4. the minimum input voltage depends on output voltage, load current and boost circuit v in boost gnd sw v in lt3507 (3a) d2 v out c3 v boost C v sw ? v out max v boost ? v in + v out v in boost gnd sw v in lt3507 (3b) d2 v out c3 v boost C v sw ? v in max v boost ? 2v in 3507 f03 d2 v in boost gnd sw v in lt3507 (3c) v out v boost C v sw ? v inb max v boost ? v inb + v in minimum value for v inb = 3v v inb > 3v c3 load current (a) 0.001 input voltage (v) 5.5 5.0 4.0 3.0 4.5 3.5 2.5 3507 f04b 1.000 0.010 0.100 t a = 25c v out = 3.3v to start to run load current (a) 0.001 input voltage (v) 8.0 7.5 6.5 5.5 4.5 7.0 6.0 5.0 4.0 3507 f04a 1.000 0.010 0.100 t a = 25c v out = 5v to start to run
lt3507 15 3507fa to ? oat, then the lt3507s internal circuitry will pull its quiescent current through its sw pin. this is acceptable if the system can tolerate a few ma of load in this state. with all three run pins grounded, the lt3507 enters shutdown mode and the sw pin current drops to <50a. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt3507 can pull large currents from the output through the sw pin and the v in pin. a schottky diode in series with the input to the lt3507, as shown in figure 5, will protect the lt3507 and the system from a shorted or reversed input. and is largest when v in = 2v out (50% duty cycle). as the second, lower power channel draws input current, the input capacitors rms current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. considering that the maximum load current from a single phase (if sw2 and sw3 are both at maximum current) is ~3a, rms ripple current will always be less than 1.5a. the high frequency of the lt3507 reduces the energy storage requirements of the input capacitor, so that the capacitance required is often less than 10f. the combi- nation of small size and low impedance (low equivalent series resistance or esr) of ceramic capacitors makes them the preferred choice. the low esr results in very low voltage ripple. ceramic capacitors can handle larger magnitudes of ripple current than other capacitor types of the same value. use x5r and x7r types. an alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1f ceramic capacitor in parallel with a low esr tantalum capacitor. for the electrolytic capacitor, a value larger than 10f will be required to meet the esr and ripple current requirements. because the input capacitor is likely to see high surge currents when the input source is applied, tan- talum capacitors should be surge rated. the manufacturer may also recommend operation below the rated voltage of the capacitor. be sure to place the 1f ceramic as close as possible to the v in and gnd pins on the ic for optimal noise immunity. a ? nal caution is in order regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, doubling the input voltage and damaging the lt3507. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. for details, see application note 88. applications information figure 5. diode d4 prevents a shorted input from discharging a backup battery tied to the output v in v in v out sw lt3507 d4 parasitic diode 3507 f05 input capacitor selection bypass the input of the lt3507 circuit with a 10f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type will work if there is additional bypassing provided by bulk electrolytic capaci- tors, or if the input source impedance is low. the following paragraphs describe the input capacitor considerations in more detail. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input ca- pacitor is required to reduce the resulting voltage ripple at the lt3507 input and to force this switching current into a tight local loop, minimizing emi. the input capacitor must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rat- ing. with three switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor rms current is not simple; however, a conservative value is the rms input current for the phase delivering the most power (v out ? i out ): i in(rms) = i out ? v out v in ?v out () v in < i out 2
lt3507 16 3507fa frequency compensation the lt3507 uses current mode control to regulate the output. this simpli? es loop compensation. in particular, the lt3507 does not depend on the esr of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. the components tied to the v c pin provide frequency compensation. generally, a capacitor and a resistor in series to ground determine loop gain. in addition, there is a lower value capacitor in parallel. this capacitor ? lters noise at the switching frequency and is not part of the loop compensation. loop compensation determines the stability and transient performance. designing the compensation network is a bit complicated and the best values depend on the application and the type of output capacitor. a practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. check stability across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. application note 76 is an excellent source as well. figure 6 shows an equivalent circuit for the lt3507 control loop. the error amp is a transconductance ampli? er with ? nite output impedance. the power section, consisting of the modulator, power switch and inductor is modeled as a transconductance ampli? er generating an output current proportional to the voltage at the v c pin. the gain of the power stage (g mp ) is 5s for channel 1 and 3.6s for chan- nels 2 and 3. note that the output capacitor integrates this current and that the capacitor on the v c pin (c c ) integrates the error ampli? er output current, resulting in two poles in the loop. in most cases, a zero is required and comes either from the output capacitor esr or from a resistor in series with c c . this model works well as long as the inductor current ripple is not too low ( i ripple > 5% i out ) and the loop crossover frequency is less than f sw /5. a phase lead capacitor (c pl ) across the feedback divider may improve the transient response. shutdown the run pins are used to place the individual switch- ing regulators and the internal bias circuits in shutdown mode. when all three run pins are pulled low, the lt3507 is in shutdown mode and draws less than 1a from the input supply. when any run pin is pulled high (>1.5v) the internal reference, ldo and selected channel are all turned on. the run pins draw a small amount of current to power the reference. the current is less than 3a at 1.8v, so the run pin can be driven directly from 1.8v logic. the run pins are rated up to 36v and can be connected directly to the input voltage. a run pin cannot be pulled up by logic powered by its own output, i.e., run1 cant be pulled up by logic powered by out1. power good indicators the pgood pin is the open-collector output of an internal comparator. pgood remains low until the fb pin is within 10% of the ? nal regulation voltage. tie the pgood to any supply with a pull-up resistor that will supply less than 200a. note that this pin will be open when the lt3507 is in shutdown mode (all three run pins at ground) regard- less of the voltage at the fb pin. pgood is valid when the lt3507 is enabled (any run pin is high) and v in is greater than ~3.5v. applications information figure 6. loop response model C + v fb 800mv v sw v c lt3507 gnd 3507 f06 r1 output esr c f c c r c 500k error amplifier fb r2 c1 c1 current mode power stage g mp 330 s + polymer or tantalum ceramic c pl
lt3507 17 3507fa output sequencing the lt3507 outputs can be sequenced in several ways. the circuits in figure 7 show some examples of these. in each case channel 1 starts ? rst, followed by channel 2, then channel 3. the sequence shown is not a requirement; the lt3507 can sequence the channels in any order. note that these circuits sequence the outputs during start-up. when shut down the three channels turn off simultaneously. the most obvious method is to bring the run pins up individually in the sequence desired (figure 7a). this is the ideal solution if full independent control of all three channels is needed. this is also a simple solution, but it does require three logic inputs. another possibility is to use the soft-start feature to slow the start-up of speci? c channels (figure 7b). all three run pins are tied together and the difference in soft-start ca- pacitance will determine the start-up sequence. the larger capacitor on channel 2 slows its start-up with respect to channel 1, and channel 3 is even slower. the capacitor on the delayed channel should be at least twice the value of the capacitor on the faster channel. a larger ratio may be required, depending on the output capacitance and load on each channel. make sure to test the circuit in the system before deciding on ? nal values for these capacitors. also remember that the delayed channels will start rising right away, just at a slower rate than the faster channels. the pg pins can be also used to sequence the three out- puts. in figure 7c, the pg pins drive the run pins directly. channel 2 will be held off until channel 1 is in regulation and channel 3 is held off until channel 2 is in regulation. the resistors pull up to v insw so that there is no current draw in shutdown. they should be sized to provide at least 1a into the run pin. the capacitors keep channels 2 and 3 off until the power good comparators are functioning (the power good comparators are disabled in shutdown). the fets are necessary to insure the run2 and run3 pins are held low during shutdown. in figure 7d, the pg pins pull down the trk/ss pins of the delayed channels. this is a simple solution requiring no extra components. channel 2 is held off by the pg1 output pulling trk/ss2 down until channel 1 is at 90% of its ? nal value. pg1 then goes high impedance and allows the channel 2 soft-start circuit to charge the soft-start capacitor bringing channel 2 up. similarly, channel 3 is held off by pg2. the circuits in figure 7a and 7b leave the power good indicators free. however, the circuits in figures 7c and 7d have another advantage. as well as sequencing the outputs at start-up, they also disable the slaved channels applications information figure 7. output sequencing run1 run2 run3 trk/ss1 trk/ss2 trk/ss3 lt3507 c 2c 4c (7b) run1 run2 run3 run1 run2 run3 lt 3 5 0 7 (7a) run2 pg1 lt 3 5 0 7 v in (7e) doesnt work! run1 run run v insw pg1 run2 run3 pg2 3507 f07 lt3507 (7c) run1 run2 run3 trk/ss1 pg1 trk/ss2 pg2 trk/ss3 lt3507 (7d) run
lt3507 18 3507fa applications information figure 8. two different modes of output voltage tracking figure 9. setup for coincident and ratiometric tracking figure 10. equivalent input circuit of error ampli? er if the master channel falls out of regulation (due to a short circuit or a collapsing input voltage). finally, be aware that the circuit in figure 7e does not work , because the power good comparators are disabled in shutdown. output voltage tracking the lt3507 allows the user to program how the output ramps up by means of the trk/ss pins. through these pins, any channel output can be set up to either coinci- dently or ratiometrically track any other channel output. this example will show the channel 2 output tracking the channel 1 output, as shown in figure 8. the trk/ss2 pin acts as a clamp on channel 2s reference voltage. v out2 is referenced to the trk/ss2 voltage when the trk/ss2 < 0.8v and to the internal precision reference when trk/ ss2 > 0.8v. to implement the coincident tracking in figure 8a, connect an extra resistive divider to the output of channel 1 and connect its midpoint to the trk/ss2 pin (figure 9). the ratio of this divider should be selected the same as that of channel 2s feedback divider (r5 = r3 and r6 = r4). in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 8b, change the extra divider ratio to r5 = r1 and r6 = r2 + r. the extra resistance on r6 should be set so that the trk/ss2 voltage is 1v when v out1 is at its ? nal value. the need for this extra resistance is best understood with the help of the equivalent input circuit shown in figure 10. at the input stage of the error ampli? er, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same amplitude. in the coincident mode, r1 r2 = v out1 0.8 ?1, r3 r4 = v out2 0.8 ?1 ? ? ? ? ? ? r5 r1 r6 r2 v out2 r4 r3 tracking setup to v fb1 pin to trk/ss2 pin to v fb2 pin v out1 coincident r3 r4 r5 = r6 = ratiometric r1 r1 v out1 /1v C 1 selecting values for r5 and r6 time (8a) coincident tracking v out1 v out2 output voltage time 3507 f08 (8b) ratiometric tracking v out1 v out2 output voltage 1 a C + i i d1 trk/ss 0.8v fb d2 d3 3507 f10 ea2
lt3507 19 3507fa the trk/ss2 voltage is substantially higher than 0.8v at steady state and effectively turns off d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb2 and the internal precision 0.8v reference. in the ratiometric mode with r6 = r2, trk/ss2 equals 0.8v at steady state. d1 will divert part of the bias current and make v fb2 slightly lower than 0.8v. although this error is minimized by the exponential i-v characteristic of the diodes, it does impose a ? nite amount of output voltage deviation. further, when channel 1s output experiences dynamic excursions (under load transient, for example), channel 2 will be affected as well. setting r6 to a value that pushes the trk/ss2 voltage to 1v at steady state will eliminate these problems while providing near ratiometric tracking. the example shows channel 2 tracking channel 1, however any channel may be set up to track any other channel. if a capacitor is tied from the trk/ss pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. this results in a ramp at the output, limiting the inductor current and therefore input current during start-up. a good value for the soft-start capacitor is c out /10,000, where c out is the value of the output capacitor. multiple input supplies v in1 , v in2 and v in3 are independent and can be powered with different voltages provided v in1 is present when v in2 or v in3 is present. each supply must be bypassed as close to the v in pins as possible. for applications requiring large inductors due to high v in to v out ratios, a 2-stage step-down approach may reduce inductor size by allowing an increase in frequency. a dual step-down application steps down the input voltage (v in1 ) to the highest output voltage, then uses that voltage to power the other outputs (v in2 and v in3 ). v out1 must be able to provide enough current for its output plus the input current at v in2 and v in3 when v out2 and v out3 are at maximum load. the typical applications section shows a 36v to 15v, 1.8v and 1.2v 2-stage converter using this approach. for applications with multiple voltages, the lt3507 can accommodate input voltages as low as 3v on v in2 and applications information v in3 . this can be useful in applications regulating outputs from a pci express bus, where the 12v input is power limited and the 3.3v input has power available to drive other outputs. in this case, tie the 12v input to v in1 and the 3.3v input to v in2 and v in3 . low dropout regulator the low dropout regulator comprises an error amp, loop compensation and a base drive amp. it uses the same 0.8v reference as the switching regulators. it requires an external npn pass transistor and 2.2f of output capaci- tance for stability. the dropout characteristics will be determined by the pass transistor. the collector-emitter saturation characteristics will limit the dropout voltage. table 4 lists some suitable npn transistors with their saturation speci? cations. the base drive voltage has a maximum voltage of 5v. this will limit the maximum output of the regulator to 5v C v besat where v besat is the base-emitter saturation voltage of the pass transistor. table 4. npn pass transistors and saturation characteristics part number v cesat v besat i c (ma) i b (ma) on semiconductor nss30071 0.25 0.85 500 5 nss30101 0.2 0.85 1000 10 fairchild ksc3265 0.4 500 20 the ldo is always on when any of the switcher channels is on. the ldo may be shut down if it is unused by pull- ing the fb4 pin up with a 30a current source. the fb4 pin will clamp at about 1.25v and the ldo will shut off reducing power consumption. this pull-up can be sourced from one of the lt3507 outputs provided that channel is always on when the other channels are on. the output stage of the ldo will drive the npn base from the bias voltage if it is at least 0.8v above the ldo drive voltage. fb resistor network the output voltage of the ldo regulator is programmed with a resistor divider (refer to block diagram) between the
lt3507 20 3507fa applications information emitter of the external npn pass resistor and the feedback pin, fb4. choose the resistors according to r1 = r2 v out4 800mv ? 1 ? ? ? ? ? ? the parallel combination of r1 and r2 should be 10k or less to avoid bias current errors. programmable overvoltage and undervoltage lockout the lt3507 provides two input pins that allow user-pro- grammable overvoltage and undervoltage lockout. both the trip levels and hysteresis can be set by resistor values. v insw provides a switched v in1 to minimize power con- sumption in shutdown. v insw is connected to v in1 when the lt3507 is operating, with a saturation voltage of about 0.3v. it is high impedance when the lt3507 is in shutdown (all three run pins low). the programmable lockout is a pair of comparators with the trip level set at 1.2v. the ovlo comparator trips when the ovlo pin exceeds 1.2v while the uvlo comparator trips when the uvlo pin drops below 1.2v. these com- parators shut down all four regulators until the input voltage recovers. the comparators also activate current sources that gener- ate hysteresis to eliminate chatter. the uvlo comparator activates a 10a current sink on the uvlo pin. the ovlo comparator activates a 10a current source on the ovlo pin. these currents generate hysteresis voltage through the resistance of the divider string. figure 11 shows a typical connection. the threshold voltages are: v ovth = 0.3v + 1.2v ? 1 + r3 r4 ? ? ? ? ? ? v uvth = 0.3v + 1.2v ? 1 + r1 r2 ? ? ? ? ? ? the hysteresis voltages are: v ovhyst = 10a ? r3 v uvhyst = 10a ? r1 if the overvoltage lockout is not used, the ovlo pin must be tied to ground. if the undervoltage lockout is not used, the uvlo pin must be tied to v insw . figure 11. undervoltage and overvoltage lockout circuit C + C + 1.2v uvlo uvlo v insw r3 r4 r1 r2 ovlo 10a 10a ovlo 3507 f11 pcb layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 12 shows the high current paths in the step-down regula- tor circuit. note that in the step-down regulators large, switched currents ? ow in the power switch, the catch diode and the input capacitor. the loop formed by these components should be as small as possible. place these components, along with the inductor and output capacitor, on the same side of the circuit board and connect them on that layer. place a local, unbroken ground plane below these components and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor c2. additionally, keep the sw and boost nodes as small as possible. figure 13 shows an example of proper pcb layout.
lt3507 21 3507fa figure 12. subtracting the current when the switch is on (12a) from the current when the switch is off (12b) reveals the path o f the high frequency switching current (12c) keep this loop small. the voltage on the sw and boost nodes will also be switched; keep these nodes as small as possible. finally, make sure the circuit is shielded with a local ground plane applications information figure 13. power path components and topside layout v in sw gnd (12a) v in v sw c1 d1 c2 3507 f12 l1 sw gnd (12c) v in sw gnd (12b) i c1 thermal considerations the high output current capability of the lt3507 will require careful attention to power dissipation of all the components to insure a safe thermal design. the pcb must provide heat sinking to keep the lt3507 cool. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the lt3507. place additional vias near the catch diodes. adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. with these steps, the thermal resistance from die (or junction) to ambient can be reduced to ja = 34c/w or less. with 100 lfpm air? ow, this resistance can fall by another 25%. further increases in air? ow will lead to lower thermal resistance.
lt3507 22 3507fa the maximum allowed power dissipation by the lt3507 can be determined by: p diss(max) = t j(max ) ?t a ja where t jmax is the maximum die temperature of 125c (150c for h-grade). however, take care in determining t a since the catch diodes also dissipate power and must be located close to the lt3507. another potential heat source is the ldo pass transistor. in a compact layout the pass transistor will be located close to the lt3507. the inductors will also dissipate some power due to their series resistance and they must be close to the lt3507. all of these heat sources will increase the effective ambient temperature seen by the lt3507. a thorough analysis of eight heat sources in a small pcb area is beyond the scope of this data sheet, however a number of thermal analysis programs are available to calculate the temperature rise in each component (such as pcanalyze from k&k associates or betasoft from mentor). the power dissipation of each component will be needed to accurately calculate the thermal characteristics of the system. the contributors to power dissipation inside the lt3507 are switch dc loss, switch ac loss, boost current, quiescent current and ldo drive current. the total dissipation within the lt3507 can be expressed as: p diss = p swdci + p swaci + p bsti () + p q + p ldo i = 1 3 the switch dc and ac losses in channel i are: p swdci = r swi i outi () 2 v outi v ini p swaci = 17ns i outi () v ini () f () applications information where r swi is the equivalent switch resistance (0.18 for channel 1 and 0.22 for channels 2 and 3) and f is the operating frequency. the boost loss in channel i is: p bsti = v outi v boosti () i outi 50 + 0.02a ? ? ? ? ? ? v ini the quiescent loss is: p q = v in1 (i q(vin1) ) + v bias (i q(bias) ) if the bias pin does not have a voltage of at least 3v ap- plied, then v in1 must replace v bias in the equation. also, i q(vin1) can be reduced by 0.2ma (typ) if the ldo is shut off (see the ldo section). the ldo drive loss is: p ldo = (v bias ? v ldo(out) ? 0.7v) i out(ldo) pass ? ? ? ? ? ? , if v bias v ldo(out) + 1.5v or p ldo = (v in1 ? v ldo(out) ? 0.7v) i out(ldo) pass ? ? ? ? ? ? , if v bias < v ldo(out) + 1.5v where pass is the current gain of the external pass transistor. next, the power in the external components must be taken into account. the diode power is given by: p diode = v f v in ?v out ?v f () i out v in where v f is the forward drop of the diode at i out . the inductor power is: p ind = (i out ) 2 esr ind where esr ind is the inductor equivalent series resistance.
lt3507 23 3507fa the ldo pass transistor power is: p npn = i outldo (v c C v outldo ) where v c is the collector voltage on the npn pass tran- sistor. example: an lt3507 design requirements are: v in = 8v, f= 500khz v1 = 2.5v at i1 = 1.6a v2 = 3.3v at i2 = 0.8a (used for boost, bias and v4) v3 = 1.2v at i3 = 1a v4 = 3v at i4 = 0.2a (from 3.3v output) t a = 50c, t jmax = 125c ja = 34c/w schottky v f = 0.45v and inductor esr = 0.05 p diss(max) = 125 c?50 c 34 c/w = 2.2w p swdc1 = 0.18 1.6a () 2 2.5v 8v = 0.14w p swac1 = 17ns 1.6a () 8v () 500k () = 0.11w p bst1 = 2.5v 3.3v () 1.6a 50 + 0.02a ? ? ? ? ? ? 8v = 0.06w similarly, p swdc2 = 0.09w, p swac2 = 0.07w, p bst2 = 0.06w, p swdc3 = 0.03w, p swac3 = 0.07w and p bst2 = 0.03w. remember, the total current from channel 2 is i2 + i4 since the ldo pass transistor draws from v2. ignore bias and boost currents. p q = 8v 3.5ma () + 3.3v 7.5ma () = 0.05w p ldo = 8v 0.2a 100 ? ? ? ? ? ? = 0.02w applications information the total dissipation on the lt3507 is the sum of all these and is equal to 0.73w. note that this is less than half of p diss(max) . next, the power dissipation of the external components are: p diode1 = 0.45v 8v ? 2.5v ? 0.45 () 1.6a 8v = 0.46w p ind1 = 1.6a () 2 0.05 = 0.13w similarly, p diode2 = 0.24w, p ind2 = 0.05w, p diode3 = 0.36w and p ind3 = 0.05w. and ? nally: p npn = 0.2a(3.3v C 3v) = 0.06w thus the total power dissipated by the lt3507 and external components is 2.08w. the thermal analysis will use these power dissipations to calculate the internal component temperatures. make sure that none of the components exceed their rated temperature limits. related linear technology publications application notes 19, 35, 44, 76 and 88 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1375 data sheet has a more extensive discussion of output ripple, loop compensation, and stability testing. design note 318 shows how to generate a dual polarity output supply using a buck regulator.
lt3507 24 3507fa typical applications 3.3v, 5v and 12v from a 24v input with ratiometric tracking v in1 boost1 uvlo ovlo boost3 sw3 fb3 v c3 bias drive fb4 pgood1 pgood2 pgood3 pgood1 pgood2 pgood3 sw1 fb1 v c1 trk/ss1 trk/ss2 trk/ss3 boost2 0.1 f 10 f 50v 22 f d1 16.2k 1000pf 1.5nf 41.2k l1 3.3 h v out1 3.3v 2a v in 21v to 27v v out2 5v 1.2a l2 6.8 h l3 10 h bat54 v in2 v in3 v insw 100k 49.9k 4.53k ovlo = 29v uvlo = 16v 100k 4.32k v out1 13.3k 41.2k bat54 bat54 18.2k sw2 fb2 v c2 r t /sync trk/ss4 gnd lt3507 run1 run2 run3 0.1 f 0.1 f 22 f 10 f d2 d3 24.3k 26.7k shdn 470nf 470pf 61.9k 68.1k nc v out1 d1: on semi mbrs230lt3 d2, d3: on semi mbra130lt3 l1: coilcraft do1813h-332ml l1: coilcraft do1813h-682ml l1: coilcraft do1813h-103ml 10.7k 3507 ta02 54.9k f sw = 800khz 11.8k 100k 100k v out3 12v 1a 150k v out1
lt3507 25 3507fa typical applications 5v, 3.3v, 2.5v and 1.8v with coincident tracking v in1 boost1 uvlo ovlo boost2 sw2 fb2 v c2 bias drive fb4 pgood1 pgood2 pgood3 pgood1 pgood2 pgood3 sw1 fb1 v c1 trk/ss1 boost3 0.22 f 22 f 100 f d1 18.7k 680pf 18.7k 4.7 h v out1 1.8v 2.4a v in 6v to 36v v out3 5v 1.5a 15 h 10 h v in2 v in3 v insw 49.9k 18.2k 100k v out1 15k sw3 fb3 v c3 r t /sync trk/ss4 gnd lt3507 run1 run2 run3 0.22 f 0.22 f 22 f 22 f d2 d3 24.3k 16.2k shdn 680pf 0.01f 1000pf 53.6k l1: wrth we-pd 744 778 9004 l2: wrth we-pd 744 778 9115 l3: wrth we-pd 744 778 910 d1, d2, d3: diodes, inc. b240a q1: on semiconductor nss30101lt1g 11.5k 11.5k 24.3k 3507 ta03 105k f sw = 450khz 10.2k 2.2nf 22 f 100k 100k v out2 3.3v 1.3a v out4 2.5v 0.2a 35.7k trk/ss3 trk/ss2 trk/ss2 v out2 v out2 15k 18.7k 35.7k 11.5k trk/ss2 q1
lt3507 26 3507fa typical applications 15v, 1.8v and 1.2v 2-stage step down v in1 boost1 uvlo ovlo pgood2 pgood3 boost 2 sw2 fb2 v c2 boost3 sw3 fb3 trk/ss2 trk/ss3 pgood1 sw1 fb1 v c1 trk/ss1 bias 0.1 f 22 f d1 68.1k 31.6k 220pf 0.01f 187k l1 10 h v out1 15v 0.4a v bst 3v v in 21v to 36v l2 3.3 h v in2 v in3 v insw 49.9k 3.4k uvlo = 19v 11.5k 10.5k 10 f drive fb4 trk/ss4 r t /sync v c3 gnd lt3507 run1 run2 run3 0.1 f 33 f pgood v bst d2 13.3k shdn 1000pf d1: diodes, inc. b140a d2, d3: diodes, inc. b240a l1: tdk ltf5022t-100m1r4 l2: tdk vlcf5020t-3r3n2r0-1 l3: tdk vlcf5020t-2r2n1r7 q1: diodes inc. bc817-16 18.2k 100k 3507 ta04 54.9k f sw = 800khz v out2 1.8v 1.5a 22.6k v out2 l3 2.2 h 0.1 f 47 f v bst d3 12.7k 1000pf 30.1k 270pf 2.2 f q1 v out3 1.2v 1.5a 15.0k
lt3507 27 3507fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701) 5.00 0.10 (2 sides) note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 0.40 0.10 37 1 2 38 bottom view?exposed pad 5.15 0.10 (2 sides) 7.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0205 0.50 bsc 0.200 ref 0.200 ref 0.00 ? 0.05 recommended solder pad layout 3.15 0.10 (2 sides) 0.40 0.10 0.00 ? 0.05 0.75 0.05 0.70 0.05 0.50 bsc 5.15 0.05 (2 sides) 3.15 0.05 (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 6.10 0.05 (2 sides) 7.50 0.05 (2 sides) 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer
lt3507 28 3507fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0509 rev a ? printed in usa typical applications part number description comments lt1939 25v, 2a, 2.5mhz high ef? ciency dc/dc converter and ldo controller v in(min) = 3.6v, v in(max) = 25v, v out(min) = 0.8v, i q = 2.5ma, i sd < 10a, 3 3 dfn-10 package lt1940 dual 25v, 1.4a (i out ), 1.1mhz, high ef? ciency step-down dc/dc converter v in(min) = 3.3v, v in(max) = 25v, v out(min) = 1.20v, i q = 3.8ma, i sd < 30a, tssop16e package lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high ef? ciency step-down dc/dc converter with burst mode operation v in(min) = 3.6v, v in(max) = 38v, v out(min) = 0.78v, i q = 70a, i sd < 1a, 3 3 dfn-10, msop-10e package lt3481 34v with transient protection to 36v, 2a (i out ), 2.8mhz, high ef? ciency step-down dc/dc converter with burst mode operation v in(min) = 3.6v, v in(max) = 34v, v out(min) = 1.26v, i q = 50a, i sd < 1a, 3 3 dfn-10, msop-10e package lt3493 36v, 1.4a (i out ), 750khz high ef? ciency step-down dc/dc converter v in(min) = 3.6v, v in(max) = 36v, v out(min) = 0.8v, i q = 1.9ma, i sd < 1a, 2 3 dfn-6 package lt3500 36v, 40vmax, 2a, 2.5mhz high ef? ciency dc/dc converter and ldo controller v in(min) = 3.6v, v in(max) = 36v, v out(min) = 0.8v, i q = 2.5ma, i sd < 10a, 3 3 dfn-10 package lt3501/10 25v, dual 3a/2a (i out ), 1.5mhz high ef? ciency step-down dc/dc converter v in(min) = 3.3v, v in(max) = 25v, v out(min) = 0.8v, i q = 3.7ma, i sd = 10a, tssop-20e package lt3505 36v with transient protection to 40v, 1.4a (i out ), 3mhz, high ef? ciency step-down dc/dc converter v in(min) = 3.6v, v in(max) = 34v, v out(min) = 0.78v, i q = 2ma, i sd = 2a, 3 3 dfn-8, msop-8e package lt3506/a 25v, dual 1.6a (i out ), 575khz/1.1mhz high ef? ciency step-down dc/dc converter v in(min) = 3.6v, v in(max) = 25v, v out(min) = 0.8v, i q = 3.8ma, i sd = 30a, tssop-16e, 5 4 dfn-16 package lt3508 36v with transient protection to 40v, dual 1.4a (i out ), 3mhz, high ef? ciency step-down dc/dc converter v in(min) = 3.7v, v in(max) = 37v, v out(min) = 0.8v, i q = 4.6ma, i sd = 1a, 4 4 qfn-24, tssop-16e package lt3684 34v with transient protection to 36v, 2a (i out ), 2.8mhz, high ef? ciency step-down dc/dc converter v in(min) = 3.6v, v in(max) = 34v, v out(min) = 1.26v, i q = 850a, i sd < 1a, 3 3 dfn-10, msop-10e package lt3685 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high ef? ciency step-down dc/dc converter v in(min) = 3.6v, v in(max) = 38v, v out(min) = 0.78v, i q = 70a, i sd < 1a, 3 3 dfn-10, msop-10e package thinsot is a trademark of linear technology corporation. burst mode is a registered trademark of linear technology corporation. 12v to 5v, 3.3v, 1.8v and 1.6v with 1.5mm maximum height related parts v in1 boost1 uvlo ovlo boost3 sw3 fb3 v c3 trk/ss3 bias drive fb4 pgood1 pgood2 pgood3 pgood1 pgood2 pgood3 sw1 fb1 v c1 trk/ss1 boost2 0.1 f 10 f 33 f d1 13.3k 1000pf 1.5nf 22.6k l1 2 h v out1 1.8v 2a v in 8v to 16v v out2 3.3v 1.5a d1: diodes, inc. dfls220l d2, d3: diodes, inc. dfls120l l1: cooper sd14-2r0-r l2, l3: cooper sd14-4r5-r q1: on semi nss30071mr6t1g l2 4.5 h l3 4.5 h v in2 v in3 v insw 49.9k 49.9k 4.02k ovlo = 17v uvlo = 7v 100k 11.3k v out1 v out2 18.2k sw2 fb2 v c2 trk/ss2 r t /sync trk/ss4 gnd lt3507 run1 run2 run3 0.1 f 0.1 f 10 f d2 d3 7.32k 11.3k shdn 2000pf 1200pf 1.5nf 1.5nf 41.2k 11.8k v out2 v out2 v out1 20.0k 20.0k 3507 ta03 31.6k f sw = 1.25mhz 2.2nf 13.3k 100k 100k v out3 5v 1.4a v out4 1.6v 0.2a 22 f 10 f 61.9k q1

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